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PCI总线;300MHz高速RF波形发生器卡:

300MHz时钟频率,12位的脉冲分辨率,灵活的单通道射频(RF)脉冲信号输出。
生产厂商: 迪阳公司代理 产品型号: PBDDS-I-300-PCI
产品简介: 300MHz时钟频率,12位的脉冲分辨率,灵活的单通道射频(RF)脉冲信号输出。

PulseBlasterDDSTM is a general-purpose, intelligent, programmable, RF and TTL/CMOS pulse/pattern generator system (PCI or USB board or a portable stand-alone system).   The PulseBlasterDDSTM series of Intelligent Pulse Generation boards from SpinCore Technologies, Inc., couples SpinCore’s unique Intelligent Pulse Timing Processor core, dubbed PulseBlasterTM, with Direct Digital Synthesis (DDS) technology for use in system control and radio-frequency (RF) pulse generation.  The PulseBlasterTM processor, implemented in state-of-the-art programmable logic, provides all the necessary timing control signals required for overall system control and pulse synchronization.  By adding DDS features, PulseBlasterDDSTM can now meet all the excitation/stimuli needs of demanding users. PulseBlasterDDSTM provides users the ability to control their systems through the generation of both digital control signals and fully synchronized excitation RF pulses from a small form factor PC board, providing users a compelling price/performance proposition unmatched by any other device on the market today.

Architecture

This figure presents the general architecture of the PulseBlasterDDS-I-300 system. The major building blocks are the DDS Core and the Pulse Programming and Timing Processor Core (PP Core). The DDS Core contains a Numerically Controlled Oscillator (NCO), 8 programmable phase registers, 1024 programmable frequency registers, the AWG(Arbitrary Waveform Generator), and the adjustable attenuator.  The PP Core controls the timing of the gating pulses and provides the necessary control signals for frequency and phase registers.  The DDS and PP cores have been integrated onto a single silicon chip.  High performance DAC chips and high current output amplifiers complement the design.

Benefits of DDS Technology

  • Generation of any frequency from DC to 1/2 reference clock oscillator in milliHertz tuning steps (32 bit digital resolution)!
  • Agile relative phase control using up to 8 programmable phase registers per channel, 12-bit phase resolution.  Pipeline delay of only 3 reference clock cycles.
  • Agile, phase coherent, "zero-time" frequency switching using 1024 independent frequency registers.
  • Agile pulsed RF output, 13.3 ns resolution (300 MHz models).
  • Easy tuning of frequency outputs.
  • Greater immunity to parameter drift due to temperature.

What does SpinCore's Intelligent Pattern Generation give users?

  • Timing resolution of 13.3 ns with a 50 MHz external clock (NOTE: Timing resolution of 2.5 ns is available on non-DDS, TTL-only PulseBlasterESR boards operating up to 400 MHz).
  • 4 independent output bits.
  • Simple instruction set.
  • Memory space for up to 32k program words (VLIW, 80-bit wide).
  • External hardware and software triggering.
  • 3.3 V digital TTL/CMOS outputs, 25 mA per pin.  Output bits can be combined to increase the max. load current.
  • Multi-board synchronization.

Added benefits

  • Small size and low power consumption.
  • Low level and high level programming support.
  • Free technical support; extended support available.

Output Signals

This exciting product comes with one analog output channels and 4 TTL/CMOS channels, all independently controlled and synchronized.   The analog channel can output RF/IF frequencies down to programmable DC levels. By providing multiple options, PulseBlasterDDSTM can be your complete excitation device for NMR, NQR, MRI, or related resonance and test technologies.  If more output channels are required, multiple boards can be synchronized to provide as many digital output bits or RF/IF channels as necessary.  The frequency and phase of the RF pulses generated by the DDS output channel are under the complete control of the user and are specified through software programming. Digital sampling rates of the output waveforms up to 300 MHz are supported.

External Triggering and Cascading

PulseBlasterDDSTM can be triggered and/or reset externally via dedicated hardware lines.  The two separate lines combine the convenience of triggering (e.g., in cardiac gating) with the safety of the "stop/reset-to-zero" line.  The required control signals are active low (or short to ground).  The design also allows for multiple boards to be synchronized, easily extending the available output pattern to more bits and/or more RF/IF channels.  The "Wait-for-event" feature is standard。

型号 射频(RF)输出通道 时钟频率 内存
PBDDS-I-300-PCI  1  300 MHz  10k
PBDDS-I-300-USB  1  300 MHz  4k

 

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