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- 80 Mbytes per second (max) input transfer rate via the front panel connector (RS422/485 differential I/O transceivers)
- 200 Mbytes per second input transfer rate via the front panel connector (Pseudo ECL I/O transceivers)
- 132 Mbytes per second PCI transfer rate in burst mode.
- A single board can interface to a wide variety of external high-speed devices.
- "Deep FIFO buffers" (up to 512 Kbytes) allow data bursts to be transferred over the PCI bus independent of transfers over the cable.
- 32-Bit data transfers on the PCI bus
- On-board cable controller, FIFOs, and DMA engine provide for continuous data transfer capability.
- Data input/output clock rate up to 20 MHz (50 MHz max PECL)
- Data input/output width of 32 bits
- "Program-and-forget" DMA engine handles D32 transfers, also DMA Chaining · Interrupts available upon DMA-completion, FIFO status, cable status,
- frame-valid and line-valid
- External interrupt input line
- 7 bi-directional signals can be
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